Chapter 4 - Processor Fundamentals

4.1 Central Processing Unit (CPU) Architecture

Stored Program Concept →

• Programs must be resident in main memory
• Program is a sequence of instructions which occupy a contiguous block of memory
• Instructions and data are indistinguishable. Each instruction is fetched, decoded, executed in sequence
• A processor called the central processing unit (CPU) carries out instructions and accesses memory directly
• Programs and data are held in the same memory

CPU Architecture →

• Arithmetic Logic Unit (ALU): Responsible for mathematical, logical, shift processing. Has internal clock to synch processes
• Control Unit: Controls data flow using signals. Ensures instructions are handled correctly. Syncs steps with regular clock pulses
• Registers: Storage components with fast access times because of their proximity to the ALU. Can be general purpose or special purpose. If there is only one general purpose register, this is called the accumulator. Special purpose registers include:
  • Current Instruction Register (CIR): Holds current instruction to decode and execute
  • Index Register (IX): Holds value to modify operands in indexed addressing
  • Memory Address Register (MAR): Holds address of memory location about to read or write
  • Memory Data Register (MDR): Acts as a buffer. Holds data that has been read or will be written
  • Program Counter (PC): Holds the address of next instruction to be read
  • Status Register (SR): Individual bits/flags raised depending on condition/event
  • Cache: Commonly used commands
  • Immediate Access Store (IAS): Frequently accessed data is stored temporarily for instant access
• Buses: Parallel transmission components with each individual wire carrying a single bit. Connect CPU components
  • Address Bus: Unidirectional; Carrying memory locations
  • Data Bus: Bidirectional and carries data
  • Control Bus: Carries control signal from CPU to synchronise F-D-E cycle. Can be bidirectional or unidirectional
• Clock: Generates timing signals to synchronise events and the F-D-E cycle. Sends out regular pulses in a time interval, and each instruction is on a pulse

Factors affecting CPU performance →

• Clock speed: The number of cycles per second. A faster speed leads to more cycles executed per second and therefore faster processing. This is limited - heat can not be removed fast enough when clock speed gets too high
• Cache memory: Small amounts of fast memory
• Number of cores: Each core processes one instruction per clock pulse. Sequences of instructions split between them, so more than one instruction is executed at once, and more sequences run at once. This reduces the time taken for a task
• Word length: A fixed number of bits per address depending on processor type
• Bus Width: The number of wires/lines in a bus, each carrying a bit. Without sufficient width, data is not transmitted in 1 cycle - making the system redundant and inefficient

Computer Ports →

• Universal Serial Bus (USB): Devices automatically detected and configured (plug and play). Impossible to correct wrong. Industrial standard supported by many OS. Full duplex for USB 3.0. Later versions are backwards compatible with earlier versions. Can draw power to charge devices
• Video Graphics Array (VGA): Reads data from a computer to output device e.g. monitor, projector, TV
• High definition multimedia interface (HDMI): proprietary audio/video for uncompressed video and all audio from a HDMI-compliant source device, such as a display controller to a monitor, projector, TV, audio device

Fetch-Decode-Execute Cycle →

• The address in PC copied to MAR with address bus
• The instruction is copied from the location in the MAR to the MDR with the data bus
• The instruction moved from MDR to CIR with data bus
• The value in the PC is incremented
• The instruction is decoded by the processor using an instruction set, splitting it into the opcode and the operand. Additional data is fetched from registers and the ontrol unit sends signals to appropriate registers to begin the execute stage
• The instruction is executed by the ALU. Registers are used to hold intermediate results; the final result is stored in the accumulator, general purpose registers or memory

Register transfer notation →

MAR ← [PC]
PC ← [PC] + 1
MDR ← [[MAR]]
CIR ← [MDR]

(one bracket = value in register. double bracket = data at address in register)

Interrupts →

An interrupt is a signal from device requiring processor attention, such as:

• program fault,
• hardware fault,
• input/output request,
• user interaction,
• timing signal.

How an interrupt is dealt with →

• At the end of the current cycle for an instruction, the processor checks if the interrupt flag is raised. If so, the priority is checked. If the priority is low, the processor continues with the current cycle. If the priority is high, register contents saved and the location of the interrupt is determined. The interrupt service routine (ISR) is loaded to the PC
• After the interrupt is dealt with, there is an immediate check for further interrupts, which are dealt with by repeated execution of the ISR. At the end, lower priority interrupts re-enabled. The then processor restores registers and continues with the interrupted cycle

4.2 Assembly language

Machine Code & Assembly Language →

• Machine code is the only language the CPU recognizes. It is made up of binary code with a defined number of bits consisting of the opcode and operand. The number of bits in the opcode depends on the number of opcodes in the instruction set.
• Assembly language is a low-level language that gives processor insight. It has a one to one relationship with machine code (i.e. one line of assembly language = one line of machine code), and has faster debugging and translation. Consists of mnemonics for the opcode and characters for the operand. It is translated with assembler. However, assembly language is time-consuming to write and not a portable language.

Modes of Addressing →

Immediate	The value used is in the instruction. This is the fastest as no memory involved
Direct	The operand holds value in instruction
Indirect	The operand holds the address containing value used in instruction
Indexed	The target address is the base address + value in index register
Relative	The operand is offset from the current address where the value is stored

Instruction groups →

Data Movement	Loads data into a register and stores in memory	LDM, LDR, LDD, LDI, LDX, STO
Arithmetic Operations	Mathematical functions	ADD, INC, DEC
Comparisons & Jumps	A program might need unconditional jump, or might need to jump depending on a condition. CMP usually followed by a jump	JMP, CMP, JPE, JPN
Input & Output	Allows entry of data or display of data	IN, OUT
Ending	Return control to operating system	END

Instruction groups →

Data Movement	Loads data into a register and stores in memory	LDM, LDR, LDD, LDI, LDX, STO
Arithmetic Operations	Mathematical functions	ADD, INC, DEC
Comparisons & Jumps	A program might need unconditional jump, or might need to jump depending on a condition. CMP usually followed by a jump	JMP, CMP, JPE, JPN
Input & Output	Allows entry of data or display of data	IN, OUT
Ending	Return control to operating system	END

Special Features of Assembly Language →

• Linkers: A computer program responsible for including links from other files and placing in a single executable file, object file, library file
• Loaders: Responsible for loading programs and libraries into memory to use and prepare for execution
• Directives: Information the assembler needs to translate code. Not an instruction; tells assembler to do something. Storage reservation and control functions
• Macros: A set of instructions used repeatedly. Written independently, embedded, and called with identifier
• Comment: Not interpreted by program; help with understanding
• System Call: Message to OS kernel to allow interaction, like access to new hardware or new processes

Assemblers →

One-pass assembler: Goes through the program one line at a time and only refers to opcode table
Two-pass assembler: used for symbolic addressing

First pass	Second pass
Remove comments Create symbol table with binary codes for symbolic names and labels Create literal table for constants Identify system calls and subroutines Act upon directives Add symbolic adddress to table Expand macros Convert data items to binary	Replace symbolic addresses with absolute addresses Resolve forward references Create object code

Creating a symbol table →

• Scan instructions in sequence
• When meeting a symbolic address, check if already in table
• If not, add to symbolic address column
• If it is, check if absolute address known
• If known, enter it
• If not, leave as unknown

4.3 Bitwise manipulation

Bitwise manipulation →

Bitwise operations are fast and simple opweations performed by CPU, treating each binary digit individually.

• Logical shift: Move left and right and introduce zeroes. Doesn’t work on two’s complement as it changes the MSB
• Arithmetic shift: All digits shift, but MSB is copied down
• Circular shift: All bits move and bit at end moved back to start

Bit masking →

A mask is a number used with logical operators AND, OR, XOR to identify, remove or set a single bit or group of bits in an address or registers.

• Checking using AND: Add a mask with 0s on all bits except desired. Will be 1 if this bit is a 1
• Setting using OR: Add a mask with 0s on all bits except desired
• Flipping using XOR: Add a mask with 0s on all bits and the opposite on the desired
• Toggling using NOT: NOT flips/inverts all bits
• Clearing a digit: flip with NOT, bitwise OR on desired digit, then flip again with NOT

Instruction		Explanation
Opcode	Operand
AND	#n/Bn/&n	Bitwise AND operation of the contents of ACC with the operand
AND	[address]	Bitwise AND operation of the contents of ACC with the contents of [address]
XOR	#n/Bn/&n	Bitwise XOR operation of the contents of ACC with the operand
XOR	[address]	Bitwise XOR operation of the contents of ACC with the contents of [address]
OR	#n/Bn/&n	Bitwise OR operation of the contents of ACC with the operand
OR	[address]	Bitwise OR operation of the contents of ACC with the contents of [address]
LSL	#n	Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end
LSR	#n	Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end